1. Field of the Invention
The present invention relates generally to a method of manufacturing a package structure, and in particular to a high-density fine line structure and method of manufacturing the same.
2. The Prior Arts
One of the important challenges in the IC industry is how to keep it under a proper cost for assembling various types of functions inside a limited package form effectively, so that chips performing different functions are to reach optimal performance. However, in the applications used in the digital, analog, memory, and wireless communications fields, etc, different electrical circuits having different functionalities can produce different performance requirements and results corresponding to the production technology. Therefore, a single chip having many integrated functions may not provide the most optimal solution. As the SOC, SiP, PiP (Package-in-Package), PoP (Package-on-Package), and stack CSP technique have rapidly advanced, it can be predicted that the most capable system chip is a packaged system which can make the most of the space allowed to integrate various chips having different functions under the various different technologies and different voltage operation environments.
In detail, the system-in-package (SIP) is a package in which chips of various IC types are assembled. A new technique which is developed from the SIP is able to stack many chips inside a package module, and able to provide or integrate more functions or higher density by utilizing the third dimensional space. The stack CSP product firstly launched to the public is memory combo, and is able to stack six layers of memory chips in a BGA package. Herein, apart from the conventional wire bonding, the solder bumps or the flip-chip technique can also be used, while the interposers can be added to assist stacking, or perhaps the heat extraction can also be gradually applied.
A package of the stack chips should include dies as the building blocks which are separated from each other, but are connected with each other by conducting wires, and may include the stack of one or more memory chips, an analog chip stacked on another SOC or digital chip, and also another separate RF chip disposed on a multi-layer interconnected substrate, where these chips have different control and I/O (input/output) paths. Moreover, if there is a memory in the stacked chip, the control software can write into the non-volatile memory (NVM).
However, because the conventional fine line technique is unable to achieve any major breakthrough in technology, the manufacturing process for fabricating the more complicated package structure as described above cannot yield greater further overall package volume reductions, for meeting the growing thinner and lighter requirements of the electronic devices.
In the conventional manufacturing of the 50 μm fine pitch line circuit on the build up material such as the glass-fiber-reinforced resin material, the method includes using a 1.5-5.0 μm thin copper as the conductive layer for the pattern plating, and flash etching is performed to etch the thin copper layer with thickness of 1.5-5.0 μm. Because a rough surface of the thin copper layer is required to be combined with the glass-fiber-reinforced resin material, the rough surface structure of the thin copper layer is therefore required in the corresponding method. According to the structure, the etching operation as required is to lead to increased etching depth for processing, thereby resulting in the damage to the wire width after plating. Due to the thickness of the thin copper layer, the etching amount may not be reduced further, and therefore, high-density board having a thinner fine pitch lower than 50 μm can not be manufactured.
During plating of the nickel on the fine line circuit layer of the printed circuit board, the electrical current is transmitted into the board, and especially for the fine line circuit layer required to be electroplated, it is necessary that the electrical current may be transmitted by the conductor trace lines which are connected with the fine line circuit layer. Although the fine line circuit layer can be fully covered using the plated nickel layer by this method, the conductor trace lines are still retained in the printed circuit board after the plating, and thereby occupy the limited wiring density. In order to decrease the wiring density, the width of the conductor trace line becomes relatively narrowed, and the thickness of the plated nickel layer may not be uniform; therefore, the decrease of the width of the conductor trace line may not be suitable for use for increasing the wiring density.
In order to improve electrical performance and reducing interference, and at the same time, to increase the wiring density, the printed circuit boards currently are designed without the conductor trace lines, and the adhesion of the wire bonding region may be optimized by nickel plating the nickel, rather than by using the chemical nickel plating (or the chemical gold plating) whose reliability is not as good. Therefore, the wire bonding region made without conductor trace lines but using nickel plating method are typically manufactured by the GPP operation.
However, before performing the GPP operation, because the plated nickel layer is formed before the solder mask (SM), the area of the plated nickel layer occupied under the SM is relatively large. Because the adhesion between the SM and the plated nickel layer is poor, the relatively high requirement for reliability and thermal stability today is unable to be met by the conventional manufacturing methods.
In other manufacturing methods such as in the non-plating line (NPL) method, besides having a complex set of procedures, a specialized machine is required for use for plating the thin copper layer, and the etching parameters for the etching are difficult to control after plating the thin copper; as a result, micro shorts are often created during manufacturing, or occurring during reliability testing, resulting in unmanageable situations.
No matter which type of NPL manufacturing method is used, the fine line layer is to be defined by the un-etched metal layer, and sometimes to rely on the selective etching of the metal layer. But, according to the conventional method, the etching cannot be controlled accurately; therefore, the manufacturing of the fine line circuit cannot rely reliably upon etching, otherwise the fine pitch line circuit faces tremendous development barrier.